Successful demonstration of nonvolatile memory sub-nanosecond operation spells good news for IoT

The research group of Professor Hideo Ohno and Associate Professor Shunsuke Fukami of Tohoku University has demonstrated the sub-nanosecond operation of a nonvolatile magnetic memory device.

FIG. 1: Schematic of the structure of developed three-terminal spin-orbit torque switching device.

Recently, the concept of "Internet of Things" (IoT) - a giant network of connected devices, people and things - has been attracting a great deal of attention. Although its range of application is limited at this stage, it is expected that in the near future, IoT will be widely applied and will play important roles in fields such as security, automated driving, social infrastructure and disability aid.

An integrated circuit, or microcontroller unit, is the brain in the IoT society, where information is acquired, processed, and transmitted. Thus, development of device technologies to make integrated circuits ultralow-power and high-performance, or high-speed, is of great importance for the progress of the IoT society.

In terms of low-power, the use of nonvolatile memories is known to be effective.

On the other hand, in terms of high-performance, it has been difficult for the nonvolatile memories which are both currently available (commercialized) and under development (not commercialized yet) to achieve the speed comparable to the one realized with currently-used volatile static random access memories.

The research group at Tohoku University had previously announced that they had developed a new-structure nonvolatile magnetic memory device. The device has a three-terminal configuration, which is different from the two-terminal magnetic memory device that is just about to hit the market.

The device uses a new scheme of spin-orbit torque-induced magnetization switching, which has been predicted to be suitable for the fast control of magnetization.

Here, the group fabricated the developed new-structure device and successfully demonstrated 0.5-nanosecond operation with a sufficiently small current. The achieved speed is comparable to the highest class of static random access memories currently available.

The group members showed that the current required to switch the magnetization does not significantly change with the operation speed unlike the case for the conventional two-terminal magnetic memory devices where the required current increases as the speed increases.

They also addressed several issues of the spin-orbit torque-induced switching device. They achieved an external-field-free switching and a reduction of switching current density by improving the structure and material systems.

The present work is expected to pave the way for the realization of ultralow-power and yet high-performance microcontroller units that are indispensable for the future progress of IoT societies.

This work is supported by the ImPACT Program of CSTI, R&D Project for ICT Key Technology to Realize Future Society of MEXT, and JSPS KAKENHI Grant numbers 15K13964 and 15J04691.

Contact:
Shunsuke Fukami
Research Institute of Electrical Communication, Tohoku University
Email: s-fukamiriec.tohoku.ac.jp
Website: http://www.riec.tohoku.ac.jp/en/

[Image below] FIG. 2: Experimentally obtained switching error rate as a function of applied current density for two devices with different material systems. Duration of current pulse is 0.5 ns. For both materials, 500-times switching for 500-times trial is obtained with a sufficiently small current density.

Image Name

FIG. 1: Schematic of the structure of developed three-terminal spin-orbit torque switching device.

Published: 17 Jun 2016

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http://www.tohoku.ac.jp/en/press/successful_demonstration_of_nonvolatile... Original article from Tohoku University
http://www.riec.tohoku.ac.jp/en/ Research Institute of Electrical Communication website

Reference: 

Authors: S. Fukami, T. Anekawa, A. Ohkawara, C. Zhang and H. Ohno
Title: A sub-ns three-terminal spin-orbit torque induced switching device Conference title: 2016 Symposium on VLSI Technology
Paper number: T6-5